`include "PRV564Config.v"
`include "PRV564Define.v"
module AQRQ_TCM
#(parameter INIT_FILE="InitData.txt")
(
    input  wire                 ICache_AQ_V,      DCache_AQ_V,
    input  wire [7:0]           ICache_AQ_ID,     DCache_AQ_ID,
    input  wire [7:0]           ICache_AQ_CMD,    DCache_AQ_CMD,
    input  wire                 ICache_AQ_CI,     DCache_AQ_CI,
    input  wire                 ICache_AQ_WT,     DCache_AQ_WT,
    input  wire [15:0]          ICache_AQ_BSEL,   DCache_AQ_BSEL,
    input  wire [127:0]                           DCache_AQ_WDATA,
    input  wire [`XLEN-1:0]     ICache_AQ_ADDR,   DCache_AQ_ADDR,
    output wire                  ICache_AQ_FULL,   DCache_AQ_FULL,
    output reg                   ICache_RQ_V,      DCache_RQ_V,
    output reg  [7:0]            ICache_RQ_ID,     DCache_RQ_ID,
    output wire                  ICache_RQ_WRERR,  DCache_RQ_WRERR,
    output wire                  ICache_RQ_RDERR,  DCache_RQ_RDERR,
    output wire                  ICache_RQ_RDY,    DCache_RQ_RDY,
    output reg  [127:0]          ICache_RQ_RDATA,  DCache_RQ_RDATA,
    input  wire                 ICache_RQ_ACK,    DCache_RQ_ACK,
    input GLBi_CLK
);
reg [127:0]ramcore[1023:0];
genvar i;
wire [127:0]wb_signal,wb_src;
initial 
begin
	$readmemh(INIT_FILE,ramcore);
end
assign wb_src=ramcore[DCache_AQ_ADDR[14:5]];
generate 
for (i = 0;i<16 ;i=i+1) 
begin
    assign wb_signal[(8*(i+1)-1):(8*i)]=DCache_AQ_BSEL[i]?
                                        DCache_AQ_WDATA[(8*(i+1)-1):(8*i)]:
                                        wb_src[(8*(i+1)-1):(8*i)];
end
endgenerate

always@(posedge GLBi_CLK)
begin
    ICache_RQ_V<=ICache_AQ_V;
    ICache_RQ_ID<=ICache_AQ_ID;
    ICache_RQ_RDATA<=ramcore[ICache_AQ_ADDR[14:5]];
    DCache_RQ_V<=DCache_AQ_V;
    DCache_RQ_ID<=DCache_AQ_ID;
    DCache_RQ_RDATA<=ramcore[DCache_AQ_ADDR[14:5]];
    if(DCache_AQ_CMD==`LSU_WRITE)
        ramcore[DCache_AQ_ADDR[14:5]]<=wb_signal;
end
assign ICache_AQ_FULL=0;
assign DCache_AQ_FULL=0;
assign ICache_RQ_WRERR=0;
assign DCache_RQ_WRERR=0;
assign ICache_RQ_RDERR=0;
assign DCache_RQ_RDERR=0;
assign ICache_RQ_RDY=1'b1;
assign DCache_RQ_RDY=1'b1;
endmodule
